High speed interfaces typically employ either interpolator based tracking receivers or a more traditional PLL (Phase-Locked Loop) based tracking receivers. Both receivers use a tracking mechanism that tracks a remote transmitter's clock phase. The interpolator based receivers use timing information embedded in data edges of the remote transmitter to align a locally generated clock with the remote transmitter's clock. At start up, the tracking loop of the receiver adjusts the phase of a local clock to match the remote transmitter's clock. When the phase of the local clock substantially matches the phase of the remote transmitter's clock, the receiver locks to the remote transmitter's clock phase. The initial phase adjustment period of the receiver is typically referred to as lock time.
To reduce latency of high speed interfaces, tracking receivers can be designed to reduce lock time. In typical tracking receivers, lock time is proportional to the initial phase error and the granularity of the interpolator (i.e., the size of the phase correction steps). Because the largest lock time occurs when phase error is 180°, fine phase corrections at such a phase error can increase lock time. In contrast, large phase corrections will reduce lock time but may increase the phase error at lock condition.